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Digital Deflection Controller
SDA 9064-5
Preliminary Data Features
q Pipeline processor structure controls deflection stages q Raster alignment by keyboard or automatically q Adaptable beam current compensation for picture
NMOS IC
height and width q Protection input stops the exceeding q For double the line frequency and 100-/120-Hz vertical frequency interlaced P-DIP-40-1
Type SDA 9064-5 Circuit Description
Ordering Code Q67100-H8382
Package P-DIP-40-1
The DDC consists essentially of a processor with program ROM and RAM, ports for input and output signals and a clock rate divider that supplies the whole chip with clock signals. The processor is specially manufactured for the arithmetic operations performed in the DDC. It operates according to the pipeline principle on account of the high requirements involved with regard to time. It has two 16-bit accumulators. The 16-bit data bus and the 7-bit address bus take care of the data traffic between the processor and the ports. The size of the static RAM is 96 x 16 bits; the program ROM can store 800 16-bit instructions. The V port and the 2 port comprise counters for coarse conversion and a chain of 32 resistors for amplitute quantization of fine conversion. The 2 port further measures the position of the ZR pulses with respect to time and transfers measured data to the processor. The east/west port similarly has a counter for digital time conversion but manages without fine conversion. The 9-bit analog-to-digital converter works on the principle of successive approximation using a capacitance field. The I2C Bus interface makes it possible to read and modify deflection data in the RAM. The protective circuitry monitors inputs SS, ZR and HA2EN using comparators. The start-up circuitry has its own power and clock pulse supply. It is therefore completely independent of the other DDC functions.
Semiconductor Group
41
01.94
SDA 9064-5
Description of the Signal and Data I/O of the Digital Deflection Controller The digital deflection controller (DDC) generates horizontal-frequency, pulsewidth modulated control signals for external deflection output stages of color TV sets. The output signal for the horizontal deflection is phase-shifted, the signal for the east/west raster correction is parabolic and the signal for the vertical deflection is saw-tooth modulated. Signal computation is performed with data values from an internal memory that can be written by the I2C Bus. DDC is synchronized by means of a horizontal and a vertical input signal. The HA2 output generates the control signals for a conventional horizontal output stage. The east/west output drives the diode modulator via a switched small-signal transistor. After the integration of the output signal a linear amplifier can be connected to the output VA1 to drive the V-output stage. The above-mentioned data values which determine the raster are stored (system-specific for 45 AX picture tubes) in an integrated ROM for 50-Hz and 60-Hz vertical deflection frequencies. However, individual alignment is possible as well. The data obtained is written into a nonvolatile memory of the operating processor. During switch-on, the data is transferred via the I2C Bus to the deflection RAM in the DDC. In addition, the variable storage time of the horizontal deflection stage transistor is compensated (2 control loop), while the pulse duty factor of the driver-control signal remains constant. The horizontal deflection stage is switched off via a protective circuitry, when the voltage at input SS exceeds a given level. The start-up circuitry supplies the horizontal deflection stage transistor with control signals in the standby mode, the switch-off phase, and during system clock failure. The system includes a control loop with an analog-to-digital converter to stabilize the shape and amplitude of the vertical deflection current (V-feedback). The input signals HS2 and VS2 are supplied with double the frequency from a TV-standard conversion circuitry. The resolution enhancement filter of the VDA can be set via two outputs with the I2C Bus interface of the deflection controller. The DDC can be externally reset via a RESET input (with L level). Deflection frequencies: 100/120-Hz field frequency, 31.25/31.5-kHz line frequency. Figure 1 shows the block diagram with the interface.
Semiconductor Group
42
SDA 9064-5
Description of the Start-Up Circuitry The horizontal start-up circuitry is provided with the supply voltage of the operating processor via pin VDD S. This supply voltage is already present in the standby mode of the TV set, although the supply voltage for the horizontal driver and horizontal output stages is not yet available. During standby mode, the HA2 output signal shape corresponds to the standard mode, however, without 2 function. The H-level duration is 14.5 s and the period ranges between 31.6 and 32.55 s, depending on the tolerance of the ceramic resonator ( 1 %). After the main supply voltage VDD has been switched on and the HA2 signals of the start-up circuitry have been correlated with the HA2 signals arriving from the DDC (2 circuitry), the standard mode is selected within one frame period (max. shift is - 2.8 to + 2.55 s including all tolerances), if the following requirements are met: - The DDC supplies the start-up circuitry with HA2 signals satisfactory with respect to the period and H-level duration - The ZR-pulse threshold is not exceeded at pin SS - The supply voltage at the horizontal driver exceeds the minimal value (threshold at pin HA2EN, if connected). The standby mode is selected immediately in response to a drop in the DDC-main supply voltage and concomitant max. phase shifts of - 2.65 to + 2.8 s. The maximum period duration of HA2 with reference to LH junctions may be 36 s in the event of faults (e.g. failure of LL1.5, malfunctions in the DDC with the exception of the start-up circuitry. The switch-off time constant of VDD S should be larger than that of VDD, ensuring that the HA2 pulses are continuously supplied during a voltage glitch of VDD and exceed the duration of the horizontal output stage voltage supply during switch-off. During all operating modes, HA2 will be high for the duration of the ZR pulse. I2C Bus Protocol The DDC includes a I2C Bus port designed for the following functions: - Slave receiver - Slave transmitter Since the DDC does not include a master function, data transfers are always initiated and controlled by an external bus master. The actual data transfer is executed by the processor of the DDC serving its I2C Bus port every 32 s and receiving or transferring data in accordance with the operating mode set. A maximum of 127 memory locations is available for read/write operations via the processor of the DDC.
Semiconductor Group
43
SDA 9064-5
During the slave-receiver mode, the DDC accepts data from the I2C Bus master. A bus telegram transmitted in this mode is characterized by the following: Slave Receiver STA Slave-Addr W Ack RAM-Addr Ack Data-H Ack Data-L Ack STOP
During the slave-transmitter mode, data is transmitted from the DDC to the I2C Bus master with the I2C Bus master clock. The first data byte to be transmitted is always the status word. A bus telegram transmitted in the slave-transmitter mode is characterized by the following: Slave Transmitter STA STA R Ack STOP W NA Slave-Addr R Ack Status Ack Data-H Ack Data-L NA STOP
= Start identification = Read/write bit = high = Acknowledge = Stop identification = Read/write bit = low = No acknowledge
The slave address of the DDC is 1000110. The following information can be received by the slave receiver during this operating mode: Sub-addresses 0A to 29: 32 bytes for raster alignment at 100 and 120 Hz vertical deflection frequency Sub-addresses 2A and 2B: 2 control words with control bits for DDC and VDA
The following information can be queried by the DDC during the slave-transmitter mode:
q Status word whose bits identify the status of the DDC q Fixed raster data from the ROM q Raster alignment data from the internal RAM
Tables 1 to 4 list the sub-addresses, name and effect of the individual data. The raster size setting (e.g. east/west pin cushion with EP) usually influences other raster characteristics (e.g. picture width). This influence can be avoided by changing other data values accordingly; refer to networking list shown in table 5. The table lists the useful steps of the data values to be adjusted and the necessary adaptation of the other data (per step width) for non-iterative setting.
Semiconductor Group
44
SDA 9064-5
The adjustment program INFRARAST in conjunction with the microcontroller SDA 20160 as I2C Bus master of the TV receiver provides for user-friendly setting via remote control. When the supply voltage VDD is not present, pins SCL and SDA are in high-impedance state. When the clock LL1.5 is not present, the I2C Bus port is without function and SCL and SDA are in high-impedance state. When the supply voltage VDD is switched on (after internal power ON reset), data can be transferred via the I2C Bus port after approx. 32 s.
Semiconductor Group
45
SDA 9064-5
Table 1 I2C Bus Data of the DDC
Subaddresses 0A 0B 0C 0D 0E 0F 10 Data D7 HP 5 X VSC 55 X VSC 65 X VF 63 D6 HP 4 X VSC 54 X VSC 64 X VF 62 D5 HP 3 X VSC 53 X VSC 63 X VF 61 D4 HP 2 X VSC 52 X VSC 62 X VF 60 D3 HP 1 X VSC 51 X VSC 61 X VF 511 D2 HP 0 X VSC 50 X VSC 60 X VF 510 D1 X X X X X X VF 509 D0 X X X X X X VF 508 Horizontal picture position None Vertical S-correction during 100-Hz operating mode None Vertical S-correction during 120-Hz operating mode None Vertical upper linearity; 120-Hz adjustment values VF 6x and 100-Hz absolute values VF 5xx; 120-Hz absolute value VF 6xx = VF 5xx + 16 * VF 6x Picture height compensation VC for evaluating the beam current information ISTR and vertical picture position VS Picture width compensation HC for evaluating the beam current information ISTR and picture height PH Vertical linearity during 100-Hz operating mode East/west raster correction in the corners at 100-Hz operating mode EWC and picture width at 100-Hz operating mode PW Definition
11
VF 507
VF 506
VF 505
VF 504
VF 503
VF 502
VF 501
VF 500
12 13 14 15 16 17 18 19
VC 3 VS 507 HC 3 PH 507 VL 515 VL 507 EWC 55 PW 57
VC 2 VS 506 HC 2 PH 506 VL 514 VL 506 EWC 54 PW 56
VC 1 VS 505 HC 1 PH 505 VL 513 VL 505 EWC 53 PW 55
VC 0 VS 504 HC 0 PH 504 VL 512 VL 504 EWC 52 PW 54
VS 511 VS 503 PH 511 PH 503 VL 511 VL 503 EWC 51 PW 53
VS 510 VS 502 PH 510 PH 502 VL 510 VL 502 EWC 50 PW 52
VS 509 VS 501 PH 509 PH 501 VL 509 VL 501 PW 59 PW 51
VS 508 VS 500 PH 508 PH 500 VL 508 VL 500 PW 58 PW 50
Semiconductor Group
46
SDA 9064-5
Table 1 I2C Bus Data of the DDC (cont'd)
Subaddresses 1A 1B 1C 1D 1E 1F 20 Data D7 EP 515 EP 507 TR 515 TR 507 X VS 607 EHTH 3 D6 EP 514 EP 506 TR 514 TR 506 X VS 606 EHTH 2 D5 EP 513 EP 505 TR 513 TR 505 X VS 605 EHTH 1 D4 EP 512 EP 504 TR 512 TR 504 X VS 604 EHTH 0 D3 EP 511 EP 503 TR 511 TR 503 VS 611 VS 603 PH 611 D2 EP 510 EP 502 TR 510 TR 502 VS 610 VS 602 PH 610 D1 EP 509 EP 501 TR 509 TR 501 VS 609 VS 601 PH 609 D0 EP 508 EP 500 TR 508 TR 500 VS 608 VS 600 PH 608 East/west parabola during 100-Hz operating mode East/west trapezoidal correction during 100-Hz operating mode Vertical picture position during 120-Hz operating mode Dynamic picture width compensation EHTH for evaluating the beam current information ISTR and picture height during 120-Hz operating mode PH Vertical linearity during 120-Hz operating mode East/west raster correction in the corners during 120-Hz operating mode EWC and picture width during 120-Hz operating mode PW East/west parabola during 120-Hz operating mode East/west trapezoidal correction during 100-Hz operating mode Control word 1, control bits for outputs I2C0 ... 1 Control word 2, refer to table 2 These adresses are reserved for test operation and must not be used Switch back to normal operating mode Status word, refer to table 3 Definition
21
PH 607
PH 606
PH 605
PH 604
PG 603
PH 602
PH 601
PH 600
22 23 24
VL 615 VL 607 EWC 65
VL 614 VL 606 EWC 64
VL 613 VL 605 EWC 63
VL 612 VL 604 EWC 62
VL 611 VL 603 EWC 61
VL 610 VL 602 EWC 60
VL 609 VL 601 PW 69
VL 608 VL 600 PW 68
25
PW 67
PW 66
PW 65
PW 64
PW 63
PW 62
PW 61
PW 60
26 27 28 29 2A 2B C4-CB
EP 615 EP 607 TR 615 TR 607 X X X
EP 614 EP 606 TR 614 TR 606 X X X
EP 613 EP 605 TR 613 TR 605 X EFS X
EP 612 EP 604 TR 612 TR 604 X FS X
EP 611 EP 603 TR 611 TR 603 X RAM X
EP 610 EP 602 TR 610 TR 602 X X X
EP 609 EP 601 TR 609 TR 601 I2C1 X X
EP 608 EP 600 TR 608 TR 600 I2C0 X X
CC-CD
X
X
X X
X X
X X
X X
X X
X FD
PONRES HOFF
Semiconductor Group
47
SDA 9064-5
Table 2 Control Word 2 0 EFS dedicted by the DDC FS RAM from the internal ROM 100-Hz operating mode 100/120-Hz operating mode determined by the FS bit 120-Hz operating mode DDC uses fixed raster data from the internal RAM 1
Table 3 Status Word 2 0 PONRES after reset of bus master FD HOFF DDC recognized 100 Hz Standard HA2 function Status word is read after each DDC reset 120 Hz recognized HA2 set "high" by protective circuitry 1
Semiconductor Group
48
SDA 9064-5
Table 4 Effect of the Raster Alignment Data SubData Value addresses 0A 0C 0E 10 10 and 11 12 HP 5 ... HP 0 VSC 55 ... VSC 50 VSC 65 ... VSC 60 VF 63 ... VF 60 VF 511 ... VF 500 VC 3 ... VC 0 Range (in decimals) - 32 ... + 31 - 32 ... + 31 - 32 ... + 31 -8...+7 Effect Picture to the right ... to the left S-correction max. neg. ... max. positive S-correction max. neg. ... max. positive Line spacing small on top ... large on top (refer to table 1)
2400 ... 3600 Line spacing small on top ... large on top (refer to table 1) -8...0 V-deflection current decreases considerably/ does not decrease when increasing beam current H-deflection current decreasing considerably/ does not decrease when increasing beam current Line spacing bottom > top ... top > bottom Vertical lines in the corners facing max. outward ... max. inward Picture width max. ... min., PW must be > 0, when HC is to be effective East-West raster max. concave ... max. convex Picture wider ... narrower on bottom Considerable ... no reduction in H-deflection current with white H stripe Line spacing bottom > top ... top > bottom Vertical lines in the corners facing max. outward ... max. inward Picture width max. ... min., PW must be > 0, HC is to be effective
12 and 13 14
VS 511 ... VS 500 HC 3 ... HC 0
2600 ... 3400 Picture position bottom ... top -8...0
14 and 15 16 and 17 18 18 and 19 1A and 1B
PH 511 ... PH 500 VL 515 ... VL 500
1450 ... 2150 Picture height min. ... max. - 32768 ... + 32767
EWC 55 ... EWC 50 - 32 ... + 31 PW 59 ... PW 50 EP 515 ... EP 500 0 ... 1023 - 32768 ... ... + 32767 - 32768 ... 0 -8...0
1C and 1D TR 515 ... TR 500 1E and 1F 20 20 and 21 22 and 23 24 24 and 25 VS 611 ... VS 600 EHTH 3 ... EHTH 0 PH 611 ... PH 600 VL 615 ... VL 600
2600 ... 3400 Picture position bottom ... top
1450 ... 2150 Picture height min. ... max. - 32768 ... + 32767
EWC 65 ... EWC 60 - 32 ... + 31 PW 69 ... PW 60 0 ... 1023
Semiconductor Group
49
SDA 9064-5
Table 4 Effect of the Raster Alignment Data (cont'd) SubData Value addresses 26 and 27 28 and 29 EP 615 ... EP 600 TR 615 ... TR 600 Range (in decimals) - 32768 ... ... + 32767 - 32768 ... 0 Effect East-West raster max. concave ... convex Picture wider ... narrower on bottom
Semiconductor Group
50
SDA 9064-5
Networking Lists Table 5.1 East/West Data 100 Hz Setting: (increase) picture width Trapezoidal correction (smaller at the bottom) (Magnify) parabola Corners (facing inward) Table 5.2 East/West Data 120 Hz Setting: (increase) picture width Trapezoidal correction (smaller at the bottom) (magnify) parabola Corners (facing inward) Table 5.3 Vertical Data 100 Hz Setting: Picture position (to the top) (Magnify) picture height Linearity (top > bottom) (Magnify) S-correction Table 5.4 Vertical Data 120 Hz Setting: Picture position (to the top) (Magnify) picture height Linearity (top > bottom) (Magnify) S-correction Changes: VSC 6 - - - 2 VL 6 - - 93 - 475 PH 6 - 8 - 19 VF 6 PW 6 VS 6 - 12/16 12/16 11/16 16 - - 26 - Changes: VSC 5 - - - 1 VL 5 - - 64 - 283 PH 5 - 8 - 19 VF 5 - 12 12 11 VS 5 16 - - 26 - Changes: EWC 6 - - - 2 EP 6 - - 382 1073 TR 6 - 125 - 782 - 732 VF 6 PW 6 -2 -4 12 6 Changes: EWC 5 - - - 1 EP 5 - - 260 760 TR 5 - 102 - 634 - 618 PW 5 -2 -4 12 6
Semiconductor Group
51
SDA 9064-5
Block Diagram
Semiconductor Group
52
SDA 9064-5
Pin Configuration (top view)
Semiconductor Group
53
SDA 9064-5
Pin Definitions and Functions Pin 1 2 Symbol Function Substrate voltage Description Substrate voltage pin to connect an external smoothing capacitor for the internally generated substrate voltage.
VSUB
SS
Protective circuitry The protective circuitry switches off the horizontal output stage and blanks the picture tube. Usually a signal derived from the line flyback is injected at SS. If the input signal exceeds a given upper level, the blanking mode is enabled (sandcastle pulse with VOH 1 level) and the output HA2 goes to high. If the input signal falls below a given lower level at SS, only the blanking mode is enabled. After the protective circuitry responds via VIH 1, POR should be enabled (switch ON/OFF of VDD S). Enable/disable of HA2 pulse. Output horizontal driver The L/H transition initiates the line retrace. The output stage transistor transfer delay is compensated (2). The pulse duty factor is kept constant. During all operating modes, HA2 is high for the duration of the ZR signal. The combined key pulse SC is generated from the horizontal and vertical flyback and the burst. The pulse can be switched to continuous blanking with the protective circuitry. The pulse is a two-level pulse. The signal voltage for this input is derived from the horizontal deflection stage. The behavior of the signal voltage corresponds to the voltage at the horizontal deflection coil. The control signal for the horizontal deflection stage (HA2) is controlled in such a manner that the input signal ZR arrives at a certain location in the blanking period of the CVBS signal. The HS2 pulse is supplied by the TV-standard conversion circuitry and is used as line reference signal.
3 4
HA2EN HA2
5
SC
Sandcastle
6
ZR
Line retrace input
7
HS2
Horizontal synchronous pulse
Semiconductor Group
54
SDA 9064-5
Pin Definitions and Functions (cont'd) Pin 8 Symbol RESET Function Input for external reset signal Description The external RESET as well as power-on reset are effective in the following sections: start-up circuitry, clock divider, processor, program ROM, 2 circuitry, A/D converter. The IC goes into the 100-Hz mode and into the ROM mode of the deflection data. (The ROM mode is retained until the RAM mode is selected via the bus interface). The blanking mode is enabled via output SC. The start-up circuitry goes into the standby mode when VDDS is switched on or during external RESET. The HA2 pulses are present during an external RESET. The RAM and the OW port are not reset. The external RESET does not affect the I2C Bus port, since the port is brought into a defined state each time it is addressed via the I2C Bus interface. However, the POR bit is set in the status word. The REF outputs are not influenced by external RESET. The input VS2 is supplied by a pulse from the TV-standard conversion circuitry, which is used as picture reference signal. Ground potential Positive supply voltage Vertical feedback input The voltage drop at the feedback resistor which is proportional to the current flowing through the vertical deflection coils is used as input signal. The vertical current is adjusted to a given nominal value with this signal. Continuous blanking will be enabled via the output SC when the vertical saw-tooth current is missing. The voltage signal proportional to the beam current is used as input signal for the following purpose: By means of beam currents differing in value (change in image brightness), the high voltage is varied and thus also the deflection angle of the beam which determines the modulation of the picture width and height. Reference voltage for A/D converter Supply voltage for A/D converter Ground potential for A/D converter 27-MHz system clock 13.5-MHz-clock signal from CGC Oscillator output for start-up circuitry Oscillator input for start-up circuitry
9
VS2
Vertical synchronous pulse
10 11 12
VSS VDD
VG
13
ISTR
Input/beam current of picture tube
14 15 16 17 18 19 20
VREFA VDDA VSSA
LL1.5 LL3 O2 O1
Semiconductor Group
55
SDA 9064-5
Pin Definitions and Functions (cont'd) Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol I C0 I2C1 Test 1 Test 2 Test 3 Test 4 Test 5 Test 6
2
Function
Description General purpose output ports controlled by I2C Bus
Test
Do not connect pins
VDD VSS
Test 7 Test 8 Test 9 N.C. OWA Output east/west raster correction Test
Positive supply voltage Ground potential Do not connect pins Not connected The course of the pulse duration of the PDM signal over the picture period is that of a parabola. The course of the pulse duration is established primarily by the programmed deflection data. The saw-tooth signal required by the analog vertical output stage is generated in a digital time converter which effects the conversion of a binary data word into a pulse duty factor. An increase of resolution by the factor of 32 is effected by amplitute quantization during the rising edge of the PDM signal within a clock period (1/fT). By connecting an external capacitor, the saw-tooth voltage for the vertical output stage is generated. Do not connect pin The data traffic between SDA 9064-5 and its environment is processed on the basis of the I2C Bus standard via a 2wire interface. The interface of the SDA 9064-5 has been designed only for the slave function. The SDA 9064-5 can be addressed as transmitter or receiver. A message transmitted via the I2C Bus is defined by a start and a stop identification. The actual message comprises one or several telegrams which can be separated by repeating the start condition. A telegram consists of data with a 2byte organization, an address byte, and a status byte. Standby supply voltage
36
VA1
Vertical deflection 1
37 38 39
N.U. SCL SDA
not used I2C Bus interface
40
VDD S
Semiconductor Group
56
SDA 9064-5
Absolute Maximum Ratings Parameter Input voltage Supply voltage Substrate voltage Total power dissipation Ambient temperature range Storage temperature range Thermal resistance system-air Symbol min. Limit Values max. 6.0 6.0 0 1.7 0 - 55 70 125 36 V V V W C C K/W - 0.5 - 0.3 - 3.2 Unit
VIM VDD VSUB Ptot TA Tstg Rth SA
Characteristics TA = 25 C (all voltages are referred to VSS) Parameter Supply voltage Standby supply voltage for start-up circuitry Supply voltage for A/D converter Ripple against VSSA Substrate voltage at pin for connecting an external smoothing capacitor Ripple against VSSA Ambient temperature range Input currents Pin 3, 6, 8, 17, 20, 38, 39 Pin 7, 9, 12, 13, 18 Pin 2 Pin 6, 17, 20, 38, 39 Pin 2, 3, 8, 12, 13 Pin 7, 9, 18
1)
Symbol min.
Limit Values max. 5.5 300 5.5 15 5.5 1.5 0.5 -2 100 50 70 10 100 1000 4.5 4.5 4.5
Unit V mA V mA V mA mV V A mV C A A A A A A
VDD
4)
VDDS1) VDDA IDDA VSUB2)
-3
TA IIH IIH IIH IIL IIL IIL
0
100 - 10 - 100 - 1000
- 10
2) 3) 4)
The voltage must have reached the required operating level prior to connecting the supply voltages for VDD and the H-output stage. In addition, the voltage must glitch-free and switched off only after the H-supply voltage has been deactivated. Internally generated, however, can also be connected externally. The IDDS feedback current flows across pin 10. VDD must be switched on and off without contact chatter.
Semiconductor Group
57
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Limit Values typ. max. Unit Test Circuit
Input Signals: LL1.5 100-Hz (120-Hz) Field PAL (NTSC); TTL Input H-input voltage L-input voltage Input capacitance measured against VSS, VI = 0 V Period Pulse duty factor Skew for LL3 Transition times
VIH VIL CI
TLL1.5
2.3
VDD
0.8 5
V V pF ns ns ns
* * * 2 2 * 2
VSS
34.6 0.43 -5 2
37 0.5
39.8 0.57 5 6
tWH/TLL1.5 tSK tHL, tLH
Input Signals: LL3 100-Hz (120-Hz) Field PAL (NTSC); TTL Input H-input voltage L-input voltage Input capacitance measured against VSS, VI = 0 V Period ** Pulse duty factor Skew for LL3 Transition times
VIH VIL CI
TLL3
2.3
VDD
0.8 5
V V pF ns
* * * 2 2 *
VSS
69.2 0.43 2
74 0.5 see LL1.5
79.6 0.57 6
tWH/TLL3 tSK tHL, tLH
ns
2
* Measurement only possible with considerable effort. ** Instead of LL3, LL1.5 can be fed into this input if HS2 is clocked with LL1.5. (For tolerances see sheet for Input LL1.5).
Semiconductor Group
58
SDA 9064-5
Input Signals LL1.5
Input Signals LL3
Semiconductor Group
59
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Limit Values typ. max. Unit Test Circuit
Input Signals: HS2 100-Hz (120-Hz) Field Horizontal Sync Pulse H-input voltage L-input voltage H-pulse width Input capacitance measured against VSS, VI = 0 V Period Start-up time for LL3 Hold time for LL3 L-pulse width
VIH VIL tWH CI
THS2
2
VDD
0.8 10 864 (858)
V V TLL1.5 pF TLL1.5 ns ns TLL1.5
* * 3 * 3 4 4 4
VSS
16
tSU tIH tWL
12 2.5 16
Input Signals: VS2 100-Hz (120-Hz) Field Vertical Sync Pulse H-Input voltage L-Input voltage H-pulse width Input capacitance measured against VSS, VI = 0 V Period Start-up time
*
VIH VIL tWH CI
TVS2
2
VDD
0.8 239 10
V V THS2 pF THS2 ns
6 6 5 * 5 *
VSS
1
240 12
342
tSU
Measurement only possible with considerable effort.
Semiconductor Group
60
SDA 9064-5
Input Signals HS2
Input Signals VS2
Semiconductor Group
61
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Input Signal: ZR-Line Retrace H-input voltage L-input voltage H-pulse width Input capacitance measured against VSS, VI = 0 V Switching threshold Switching threshold** VREFA = 5.1 V Limit Values typ. max. Unit Test Circuit
VIH VIL tWH CI VS VSHA
3.5 - 0.3 4 5.5
VDD
0.8 7 10
V V s pF V V
* * 7 * * 8
1 2.5
1.8 3
2.1 3.5
* Measurement only possible with considerable effort. ** When the threshold VSHA is exceeded, status HA2 = L is not longer possible. Application note: generate pulse at ZR by means of Z-diode circuitry.
Input Signal ZR
Semiconductor Group
62
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Input Signal: VREFA Reference Voltage Input voltage (during operation) at 5.1 V on Z diode TC 1 mV/K Input current Input capacitance measured against VSS, VI = 0 V Ripple Input Signals: VG, ISTR (A/D converter inputs) Typ. input voltage VI = 1.36 V Min. input voltage VI = 1.29 V,VREFA = min Max. input voltage VI = 1.43 V,VREFA = max Input capacitance for VG Input capacitance for ISTR Sampling time*** Conversion time Conversion Data Resolution 9 bits (LSB = 1.36 V: 29 = 2.6 mV) Absolute accuracy (offset and gain errors) Non-linearity (deviation from straight line) Differential non-linearity Conversion time 4 LSB * Limit Values typ. max. Unit Test Circuit
VIH
4.84
5.1
5.36
V
*
IIL CI
2.3
5 25 0.5
mA pF mV
9 * *
VI VI
min
1.73 1.64 1.81
3.09 2.93 3.24 70 70 168/LL1.5** 798/LL1.5**
V V V pF pF s s
* * * * * * *
VI max CI CI tS tC
1/2 1/2
LSB LSB s
* * *
tC
29.5
* Measurement only possible with considerable effort. ** LL1.5 in MHz *** During the sampling time, the generator resistance must be able to charge/discharge the input capacitance from max. 70 pF to an accuracy of 9 bits (exactly V = 1.43 V).
Semiconductor Group
63
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Input Signal: SS-Protective Circuitry H-input voltage VIH VIH1 VIH VIH2 (protective circuitry does not respond) H-pulse width L-pulse width Input capacitance measured against VSS, VI = 0 V Response threshold for protective circuitry VREFA = 5.1 V Input Signal: (I2C Bus clock) H-input voltage IIH = 10 A max at VDD = min L-input voltage - IIH = 10 A Input capacitance measured against VSS, VI = 0 V
*
Limit Values typ. max.
Unit
Test Circuit
2.8
3.3
3.8
V
*
tWH tWL CI VIH 1 VIH 2
3.9 2.1
5.5 26.5 10 4 2.4 4.2 2.7
s s pF V V
* * * 10 *
VIH
3.0
VDD
V
*
VIL CI
VSS
1.5 10
V pF
* *
Measurement only possible with considerable effort
For timing and transfer modes refer to I2C Bus protocol Input Signal SS
Semiconductor Group
64
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Input Signal: HA2EN Enabling/Disabling of HA2 Pulses H-input voltage** L-input voltage** Input capacitance VI = 0 V Limit Values typ. max. Unit Test Circuit
VIH VIL CI
4
VDDS
2.9 10
V V pF
11 11 *
VSS
Input Signal: O1 Oscillator Input Start-Up Circuitry H-input voltage L-input voltage Input capacitance VI = 0 V External capacitance**** (depends on the characteristics of the ceramic resonator)
VIH VIL CI CO1 CO2
3.5
VDDS
1.5 10 30 30
V V pF pF pF
12 12 * 13 13
VSS
Input Signal: RESET Input for External Reset Signal H-input voltage*** L-input voltage*** Input capacitance VI = 0 V Input Signal O1
* Measurement only possible with considerable effort. ** Input is high (by internally pull-up resistor approx. 100 k) and HA2 pulses are enabled. Input is low and HA2 pulses are disabled. VREFA = 5.1 V *** Input is high (by internally pull-up resistor approx. 100 k), i.e. the IC is in the active mode. Input is low, i.e. the IC has been reset. **** Dependent upon characteristics of ceramic oscillator.
VIH VIL CI
2
VDD
0.8 10
V V pF
14 14 *
VSS
Semiconductor Group
65
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Bidirectional Signal: SDA (open drain I2C Bus) H-input voltage IIH = 10 A max at VDD = min L-input voltage - IIL = 10 A H-output voltage1) - IQH = 10 A L-output voltage - IQL = 2 mA H-L transition time CL = 300 pF L-H transition time2) CL = 300 pF Input capacitance measured against VSS, VI = 0 V Limit Values typ. max. Unit Test Circuit
VIH VIL VQH VQL tTHL tTLH CI
3
VDD
1.5
V V V V s s
* * * * * * *
VSS
VDD
0.4 0.5
10
pF
For timing and transfer modes refer to I2C Bus protocol Output Signals: HA2 100 Hz- (120-Hz) Field Horizontal Driver H-output voltage - IQH = 0.5 mA L-output voltage - IQL = 3 mA Limiting current3) Rise time CL = 300 pF Fall time CL = 300 pF Pulse width4) tH = constant Quantization step Delay time
* 1) 2) 3) 4)
VQH VQL Ilim tLH tHL tH t1 tD
4
VDD
0.5 10 80 80
V V mA ns ns s ns
* * * 15 15 16 * 7
VSS
13.55
14.5 2.3
15.59
3.2
10.4
s
Measurement only possible with considerable effort. Minimum output voltage depends on external pull-up resistor and the leakage current IQH. Depends on pull-up resistor. Max. permissible output current. Output is not short-circuit resistant. At maximum permissible frequency fluctuation of LL1.5.
Semiconductor Group
66
SDA 9064-5
Output Signals HA2
Output Signal: OWA
Semiconductor Group
67
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Output Signal: VA1 Vertical Deflection (short-circuit resistant against VSS) H-output voltage** - IQH = 5 A L-output voltage IQL = 1 mA Quantization steps Sum of quantization steps Clock period Limit Values typ. max. Unit Test Circuit
VQH
2
VDD - 1 V
*
VQL tQS
QS TLL1.5
VSS
1.15 32 37
1.3
V ns ns
* * * *
Output Signal: OWA (East/West raster correction) H-output voltage - IQH = 5 mA H-output voltage IQH = 5 mA Limiting current Rise time CL = 300 pF Fall time CL = 300 pF H-pulse width Delay time
VQH VQL Ilim tLH tHL t2 tD
2
VDD
0.4 10 30 30 864
V V mA ns ns
* * * 17 17
VSS
LL1.5 *
depends on 2 adjustment s circ.
* Measurement only possible with considerable effort. ** Modulation determined by ROM occupancy.
Semiconductor Group
68
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Substrate Bias Voltage VSUB Substrate (internally generated, but can be supplied externally as well) Load capacitance (recommended) measured against VSSA Ripple measured against VSSA
* Measurement only possible with considerable effort.
Limit Values typ. max.
Unit
Test Circuit
VSUB
-3
- 2.5
-2
V
18
CL
100
nF
50
mV
*
Substrate Bias Voltage
Semiconductor Group
69
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Output Signal: SC Sandcastle H-output voltage, level 2 IQH2 = - 50 A H-output voltage, level 1 IQH1 = 100 A L-output voltage IOL = 100 A Delay time with respect to ZR Delay time with respect to HS2 LL1.5 = 27 MHz Clamping pulse Rise/fall time CL = 15 pF Limiting current
*
Limit Values typ. max.
Unit
Test Circuit
VQH2 VQH1 VOL tD1ZR tD2ZR tDHS2 tclamp t Ilim
4.1 2.1
5 2.5
VDD
2.9 1 200 300
V V V ns ns s TLL1.5 ns
* * * * 19 1 * *
VSS
1.2 54 200
1.5
4
mA
Measurement only possible with considerable effort.
For reference signal V line retrace see page 85. Output Signal SC
Semiconductor Group
70
SDA 9064-5
Characteristics (cont'd) TA = 25 C; VDD = 5 V (all voltages are referred to VSS) Parameter Symbol min. Output Signal: O2 Oscillator Output Start-Up Circuitry H-output voltage - IQH = 100 A L-output voltage IQL = 200 A External capacitance Output Signals: I2C0, I2C1 H-output voltage - IQH = 0.5 mA L-output voltage IQL = 3 mA Limit Values typ. max. Unit Test Circuit
VQH VQL CO2
3.5
VDDS
1.5
V V pF
20 21
VSS
see oscillator input
VQH VQL
3
VDD
0.5
V V
22 23
VSS
Semiconductor Group
71
SDA 9064-5
Test Circuit 1 Output Signals and Phase Relationships
Semiconductor Group
72
SDA 9064-5
Test Circuit 2 Frequency and Pulse Duty Factor of LL1.5 and LL3 Apply to input LL1.5 a clock pulse varying in frequency, pulse duty factor and transition times and apply via a pulse shaper to input LL3 a clock pulse divided by a factor of 2. Monitor outputs HA2 (horizontal frequency pulses), OWA (vertical frequency parabola) and VA1 (vertical frequency sawtooth). Connect all other pins as shown in test circuit 1.
Test Circuit 3 Frequency and Pulse Duty Factor of HS2 Apply a clock pulse varying in frequency and pulse duty factor to input HS2 and monitor the time during which the pulses at output SC are synchronous with input signal HS2. Apply to input VS2 100 Hz for the 100-Hz operating mode and 120 Hz for the 120-Hz operating mode. Connect all other pins as shown in test circuit 1. Semiconductor Group 73
SDA 9064-5
Test Circuit 4 Phase of HS2 with Respect to LL3 Apply to input HS2 a clock pulse having a frequency of 13.5 MHz/432 via an adjustable phase shifter and set the phase exactly to that at which the pulses at output SC jitter with respect to HS2 by one LL3-clock pulse. Then read off the phase between HS2 and LL3. Connect all other pins as shown in test circuit 1.
Test Circuit 5 Frequency and Pulse Duty Factor of VS2 Apply to input VS2 a clock pulse varying in frequency and pulse duty factor and monitor the time during which the saw-tooth at output VA1 is synchronous with input signal VS2. Apply a clock pulse of 31.25 kHz to input HS2. Connect all other pins as shown in test circuit 1.
Semiconductor Group
74
SDA 9064-5
Test Circuit 6 Switching Threshold of VS2 Increase a DC voltage at input VS2, starting at 0 V, until the period of the saw-tooth output signal VA1 is appreciably reduced. Connect all other pins as shown in test circuit 1.
Test Circuit 7 Pulse Width of ZR Apply clock pulse LL3 divided by a factor of 432 to output HS2. Vary the feedback signal HA2 at the ZR input with the delay element (phase) and pulse shaper (pulse width) until the center of the ZR pulse with respect to time is moved compared to the HS2 signal. Connect all other pins as shown in test circuit 1. This circuit may also be used to measure the time delay tD of output signal HA2.
Semiconductor Group
75
SDA 9064-5
Test Circuit 8 Switching Threshold of ZR Increase a DC voltage starting at 0 V at input ZR until output HA2 goes to high. Connect all other pins as shown in test circuit 1.
Test Circuit 9 Input Current of VREFA Set DC voltage before the ammeter such that 5.1 V are measured at input VREFA with the voltmeter. Connect all other pins as shown in test circuit 1.
Semiconductor Group
76
SDA 9064-5
Test Circuit 10 Switching Threshold of SS Increase a DC voltage at input SS, starting at 0 V, until output HA2 goes to high. The inhibition of HA2 can be cancelled by switching VDDS on and off. Connect all other pins as shown in test circuit 1.
Test Circuit 11 Switching Threshold of HA2EN Reduce a DC voltage at input HA2EN, starting at + 5 V, until output HA2 goes to high. Connect all other pins as shown in test circuit 1.
Semiconductor Group
77
SDA 9064-5
Test Circuit 12 Switching Threshold of O1 Increase a DC voltage at input O1, starting at 0 V, until O1 and O2 are equipotential. Connect all other pins as shown in test circuit 1.
Test Circuit 13 Capacitors at O1 and O2 Vary capacitors C1 and C2 until the pulses specified for output HA2 are barely available at the output. Connect all other pins as shown in test circuit 1.
Semiconductor Group
78
SDA 9064-5
Test Circuit 14 Switching Threshold of RESET Reduce a DC voltage at output RESET, starting at + 5 V, until output SC no longer provides any pulses. Connect all other pins as shown in test circuit 1.
Test Circuit 15 Transition Times of HA2 Connect a 3.3 nF capacitor to output HA2 and measure the transition times between VQH and VQL. Convert to the load capacitance specified in the characteristics. Connect all other pins as shown in test circuit 1.
Semiconductor Group
79
SDA 9064-5
Test Circuit 16 Pulse Width of HA2 Apply to input LL1.5 a clock pulse having minimum and maximum permissible frequency (refer to characteristics of LL1.5), to input LL3 the clock pulse LL1.5 divided by a factor of 2, and to input HS2 the clock pulse LL3 divided by a factor of 432, and measure the pulse width tH of HA2. Connect all other pins as shown in test circuit 1.
Test Circuit 17 Transition Times of OWA Connect a 3.3 nF capacitor to output OWA and measure the transition times between VQH and VQL. Convert to the load capacitance specified in the characteristics. Connect all other pins as shown in test circuit 1.
Semiconductor Group
80
SDA 9064-5
Test Circuit 18 Substrate Bias Voltage Connect a 100 nF capacitor to pin VSUB and measure the negative subtrate bias voltage VSUB. Connect all other pins as shown in test circuit 1.
Test Circuit 19 Delay of SC with Respect to HS2 Apply clock pulse LL3 divided by a factor of 432 via a delay element to input HS2 and vary the delay by just over one LL3 period. Read off minimum and maximum delay tDHS2 of the clamping pulse to HS2. Connect all other pins as shown in test circuit 1.
Semiconductor Group
81
SDA 9064-5
Test Circuit 20 H Level of O2 Ground input O1. Set voltage on the ammeter so that the current specified in the characteristics flows from output O2. Read off H level at O2. Connect all other pins as shown in test circuit 1.
Test Circuit 21 L Level of O2 Apply + 5 V to input O1. Set the voltage on the ammeter so that the current specified in the characteristics flows into output O2. Measure L level at O2. Connect all other pins as shown in test circuit 1.
Semiconductor Group
82
SDA 9064-5
Test Circuit 22 H Level of I2C0 Set output I2C0 to high using the I2C Bus. Set the voltage on the ammeter so that the current specified in the characteristics flows from output I2C0. Measure H level at I2C0. Connect all other pins as shown in test circuit 1. This measuring circuit can also be used for output I2C1.
Test Circuit 23 L Level of I2C0 Set output I2C0 to low using the I2C Bus (or switch IC ON and OFF). Set the voltage on ammeter so that the current specified in the characteristics flows into output I2C0. Read off L level at I2C0. Connect all other pins as shown in test circuit 1. This measuring circuit can also be used for output I2C1.
Semiconductor Group
83
SDA 9064-5
DDC SDA 9064-5 Behavior with H-Start-Up Circuitry and Driving of the H-Output Stage during Switch-ON/OFF and Operating Voltage Glitch
Semiconductor Group
84
SDA 9064-5
Interrelation of SC, ZR and VS2
Semiconductor Group
85

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